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3.9
Serial Peripheral Interface
The device includes a Serial Peripheral Interface (SPI) to provide access to the configuration registers and digital data. Ref-
erence Section 4 for details regarding the SPI protocol and available commands.
To maximize independence between the X and Y channels, the device includes two interface blocks, one for each axis. The
X-axis interface block responds only to X-axis acceleration requests, or even addressed register commands. The Y-axis interface
block responds only to Y-axis acceleration requests, or odd addressed register commands. To the SPI master, the device oper-
ates as a single device. The internal independent blocks are transparent.
Each SPI block has an independent shift register. Once a message is received (rising edge of CS), the contents of the two
shift registers are compared. If the contents do not match, the Y-Axis SPI block will not respond, and the X-Axis SPI block will
respond with a SPI Error as shown in Table 30 . If the contents match, each SPI block decodes the message, and the appropriate
block enables DO for a response during the next SPI message.
Figure 33 shows an internal diagram of the SPI.
Registers
X SPI
If Bit 13 == ‘1’
If Bit 13 = ‘0’
& Bit 14 == ‘0’
& A0 == ‘0’
SPI Master
Even Address Regs
X SPI Shift Register
X-Axis Raw Data
CS_M
CS
CS
X-Axis OC Data
SPI Mismatch Error (SPI Error)
SCLKM SCLK
MOSI
MOSIM
MISO
MISOM
SCLK
MOSI
MISO
I/O
Odd Address Regs
Y-Axis Raw Data
Y SPI Shift Register
Y-Axis OC Data
If Bit 13 == ‘1’
Y SPI
If Bit 13 = ‘0’
& Bit 14 == ‘1’
& A0 == ‘1’
Figure 33. SPI Diagram
MMA65xx
Sensor
42
Freescale Semiconductor, Inc.
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